1. Field of the Invention
The invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the same.
2. Background Art
Thus far, nonvolatile semiconductor memory devices such as flash memory have been fabricated by integrating elements two-dimensionally on the surface of a silicon substrate. In order to increase the memory capacity of such flash memories, it is necessary to reduce the dimension of each element to allow downscaling. However, such downscaling is becoming difficult these days in terms of cost and technique.
In order to solve this problem, many methods of integrating elements three-dimensionally are proposed. In particular, a collective patterned three-dimensional stacked memory having high productivity is promising (see JP-A 2007-266143 (Kokai), for example). In this technique, electrode films and insulating films are alternately stacked on a silicon substrate to form a stacked body, and then through holes are formed in the stacked body by collective processing. Subsequently, a charge storage layer is formed on the side surface of the through holes, and silicon is buried in the through holes to form a silicon pillars. Thereby, a memory cell is formed at the intersection of each of the electrode films and the silicon pillar. Further, the end portion of the stacked body is patterned into a staircase shape; an interlayer insulating film is provided around the stacked body so as to overlap the staircase-shaped end portion; and a contact is buried in the interlayer insulating film so as to be connected to the end portion of each of the electrode films. Then, a plurality of metal interconnects are provided above the interlayer insulating film and are each connected to the end portion of each of the electrode films via the contact. Thereby, the electric potential of each of the electrode films can be controlled independently via the metal interconnect and the contact.
In the collective patterned three-dimensional stacked memory, by controlling the electric potentials of each electrode film and each silicon pillar, a charge can be transferred between the silicon pillar and the charge storage layer, and thereby information can be recorded. In this technique, a plurality of electrode films are stacked on the silicon substrate to reduce the chip area per bit, and it allows cost reduction. Furthermore, the three-dimensional stacked memory can be formed by processing the stacked body collectively; therefore, the number of lithography steps does not increase even if the number of stacked layers increases, and an increase in cost can be suppressed.
As one of the examples of the collective patterned three-dimensional stacked memory, a structure in which one semiconductor pillar is divided into two pieces along the extending direction thereof and the divided semiconductor pillars are used as separate memory cells is disclosed (see JP-A 2008-10868 (Kokai), for example). It is conceivable that this structure improves the integration degree. However, there is room for improvement in view of the actual processing accuracy.